Recently, liquid crystal panels have been used widely in various electronic equipment such as mobile telephones, PDAs, car navigation systems, personal computers, televisions, video cameras, and digital cameras. Liquid crystal panels have advantages of thinness, lightweight, and low-power consumption. As for methods of mounting drivers on such liquid crystal panels, a so-called COG (Chip On Glass) method has been known in which a driver is mounted directly on one of a pair of substrates opposed to each other (for example, active matrix substrate) via a liquid crystal material (for example, see Patent Documents 1 to 5). Using this COG method allows the liquid crystal panel to have thinness, compactness, lightweight, and fineness between lines and between terminals. In particular, recently, compact liquid crystal panels with fineness have been demanded, which results in the increment of disconnection and short circuit of lines formed outside a display region. In other words, in a mounting step, mounting drivers on defective liquid crystal panels causes a loss of material costs and operating costs, and therefore, it becomes more important to inspect disconnection/short circuit of lines on the active matrix substrate in an inspection step during manufacture or the like of the liquid crystal panel.
FIG. 14 is a plan view showing a schematic configuration of a COG type liquid crystal panel 100 that has been used conventionally (for example, see Patent Document 6). As shown in FIG. 14, the liquid crystal panel 100 includes an active matrix substrate 200 and a counter substrate 300 opposed to the active matrix substrate 200. A liquid crystal material (not shown) is interposed between the active matrix substrate 200 and the counter substrate 300.
The active matrix substrate 200 has a display region 201, a terminal arrangement region 202, and a frame-shaped wiring region 203 that is positioned in an outer side of the display region 201 and surrounds the display region 201. Note here that one edge of the liquid crystal panel 100 is referred to as a first edge S1 (the lower edge in FIG. 14), edges on the left and right sides with respect to the first edge S1 are referred to as a second edge S2 and a third edge S3, respectively, and the edge opposed to the first edge S1 is referred to as a fourth edge S4.
The display region 201 is provided with a plurality of scanning lines 204, a plurality of data lines 205, and a plurality of storage capacity lines 206. Here, the plurality of scanning lines 204 that are formed in the display region 201 on the fourth edge S4 side (the upper side in FIG. 14) (hereinafter, referred to as “upper scanning lines”) respectively have input ends 207 for scanning signals on one end side. The plurality of scanning lines 204 that are formed in the display region 201 on the first edge S1 side (the lower side in FIG. 14) (hereinafter, referred to as “lower scanning lines”) respectively have input ends 208 for scanning signals on the other end side. Further, the plurality of data lines 205 respectively have input ends 209 for data signals on one end side.
In the terminal arrangement region 202, a plurality of scanning terminals 210 and a plurality of data terminals 211 are arranged.
In the frame-shaped wiring region 203, a plurality of first connection lines 212 connecting the input ends 207 of the upper scanning lines 204 for scanning signals with the scanning terminals 210, a plurality of second connection lines 213 connecting the input ends 208 of the lower scanning lines 204 for scanning signals with the scanning terminals 210, and a plurality of third connection lines 214 connecting the input ends 209 of the data lines 205 for data signals with the data terminals 211.
Further, in the frame-shaped wiring region 203, an upper disconnection inspection line 215 for inspecting disconnection of the upper scanning lines 204 and the first connection lines 212, and an upper disconnection inspection pad 216 connected with the upper disconnection inspection line 215 are formed. Thus, disconnection of the upper scanning lines 204 and the first connection lines 212 can be detected on the liquid crystal panel 100. Further, in the frame-shaped wiring region 203, a lower disconnection inspection line 217 for inspecting disconnection of the lower scanning lines 204 and the second connection lines 213, and a lower disconnection inspection pad 218 connected with the lower disconnection inspection line 217 are formed. Thus, disconnection of the lower scanning lines 204 and the second connection lines 213 can be detected on the liquid crystal panel 100.
Further, in the frame-shaped wiring region 203, a plurality of first switching elements 219, a first switching element control line 220 through which on/off control signals can be fed to the plurality of first switching elements 219, a first upper short circuit inspection line 221 for inspecting short circuit of the odd-numbered upper scanning lines 204 and the odd-numbered first connection lines 212, and a second upper short circuit inspection line 222 for inspecting short circuit of the even-numbered upper scanning lines 204 and the even-numbered first connection lines 212 are formed. Here, the first switching element control line 220 is connected with a control pad 223. The first upper short circuit inspection line 221 is connected with a first upper short circuit inspection pad 224. The second upper short circuit inspection line 222 is connected with a second upper short circuit inspection pad 225. Thus, short circuit of the upper scanning lines 204 and the first connection lines 212 can be detected on the liquid crystal panel 100.
Further, in the frame-shaped wiring region 203, a plurality of second switching elements 226, a second switching element control line 227 through which on/off control signals can be fed to the plurality of second switching elements 226, a first lower short circuit inspection line 228 for inspecting short circuit of the odd-numbered lower scanning lines 204 and the odd-numbered second connection lines 213, and a second lower short circuit inspection line 229 for inspecting short circuit of the even-numbered lower scanning lines 204 and the even-numbered second connection lines 213 are formed. Here, the second switching element control line 227 is connected with a control pad 230. The first lower short circuit inspection line 228 is connected with a first lower short circuit inspection pad 231. The second lower short circuit inspection line 229 is connected with a second lower short circuit inspection pad 232. Thus, short circuit of the lower scanning lines 204 and the second connection lines 213 can be detected on the liquid crystal panel 100.
Further, in the frame-shaped wiring region 203, a plurality of third switching elements 233, a third switching element control line 234 through which on/off control signals can be fed to the plurality of third switching elements 233, a first data inspection line 235 for inspecting disconnection/short circuit of the data line 205 for R(red), a second data inspection line 236 for inspecting disconnection/short circuit of the data line 205 for G(green), and a third data inspection line 237 for inspecting disconnection/short circuit of the data line 205 for B(blue) are formed. Here, the third switching element control line 234 is connected with a control pad 238. The first data inspection line 235 is connected with a first data inspection pad 239. The second data inspection line 236 is connected with a second data inspection pad 240. The third data inspection line 237 is connected with a third data inspection pad 241. Thus, disconnection/short circuit of the data lines 205 can be detected on the liquid crystal panel 100.
As described above, in the inspection step during manufacture or the like of the liquid crystal panel 100, disconnection/short circuit of lines in the active matrix substrate 200 can be inspected.
By the way, recently, the vertical and horizontal pixels of the display screens of liquid crystal panels used in compact electronic equipment such as mobile telephones, PDAs, and PHSs are now making a shift from 160×120 QQVGAs (Quarter Quarter Video Graphics Array) and 176×144 QCIFs (Quarter Common Intermediate Format) to 320×240 QVGAs (Quarter Video Graphics Array) and further to 640×480 VGAs (Video Graphics Array). Accordingly, the numbers of the scanning terminals 210 and the data terminals 211 to be arranged in the terminal arrangement region 202 of the liquid crystal panel 100 are increased. However, in order to meet the demand for a thinner, smaller, lighter, and low-cost liquid crystal panel 100, the numbers of the scanning terminals 210 and the data terminals 211 to be arranged in the terminal arrangement region 202 should be increased without extending the conventional terminal arrangement region 202. Consequently, spacings between terminals to be arranged in the terminal arrangement region 202 have gradually been reduced these days.
Here, in the aforementioned liquid crystal panel 100, in order to detect short circuit of the lower scanning lines 204 and the second connection lines 213 on the liquid crystal panel 100, in a section E of FIG. 14, it is necessary to form the second switching element control line 227, the first lower short circuit inspection line 228, and the second lower short circuit inspection line 229 in the terminal arrangement region 202. That is, at least three lines 227 to 229 provided for inspecting short circuit of the lower scanning lines 204 and the second connection lines 213 should have been formed in the terminal arrangement region 202. However, owing to the recent trend of reducing spacings between terminals to be arranged in the terminal arrangement region 202, it becomes difficult to form the three lines 227 to 229 in the terminal arrangement region 202. Therefore, in order not to form the three lines 227 to 229 in the terminal arrangement region 202, a liquid crystal panel 100a shown in FIG. 15 or a liquid crystal panel 100b shown in FIG. 16 has been considered.
In the liquid crystal panel 100a shown in FIG. 15, as compared with the liquid crystal panel 100 shown in FIG. 14, the three lines 227 to 229 are formed closer to an outer side (third edge S3) of the frame-shaped wiring region 203 than the first connection lines 212. Thereby it is possible not to form the three lines 227 to 229 in the terminal arrangement region 202. Further, in the liquid crystal panel 100b shown in FIG. 16, as compared with the liquid crystal panel 100 shown in FIG. 14, the three lines 227 to 229 are once led out to the fourth edge S4 side and then is led back to the first edge S1, in stead of directly being led out to the first edge S1. Thereby, likewise the liquid crystal panel 100a shown in FIG. 15, the three lines 227 to 229 are not formed in the terminal arrangement region 202.
However, in the liquid crystal panel 100a shown in FIG. 15, since the three lines 227 to 229 are formed closer to the outer side of the frame-shaped wiring region 203 than the first connection lines 212, lead-out lines 242 that are led out from the one end side of the lower scanning lines 204 to the third edge S3 side are newly formed in the frame-shaped wiring region 203. Because of this, as shown in FIG. 15, the first connection lines 212 and the lead-out lines 242 cross each other in an intersection portion A, which results in the generation of electric capacities in the intersection portion A. At this time, when observing one of the first connection lines 212, it crosses all the lead-out lines 242 connected with the lower scanning lines 204, and generates electric capacities at respective intersections. Meanwhile, when observing one of the lead-out lines 242 connected with the lower scanning lines 204, it crosses all the first connection lines 212, and generates electric capacities at respective intersections. Because of this, loads are increased both in the upper scanning lines 204 and the lower scanning lines 204, and therefore, scanning signals are unable to achieve a desired potential during a scanning period, or a period in which the desired potential is maintained is shortened. Consequently, data signals cannot be charged fully in picture elements, whereby the display quality is decreased.
Further, when the number of the upper scanning lines 204 and the number of the lower scanning lines 204 are different from each other, a load applied to the upper scanning lines 204 and a load applied to the lower scanning lines 204 are different. Thereby a potential to be achieved by the upper scanning lines 204 and a potential to be achieved by the lower scanning lines 204 will be different. Accordingly, a charging rate of the picture elements corresponding to the upper scanning lines 204 and a charging rate of the picture elements corresponding to the lower scanning lines 204 will be different. That is, in the picture elements corresponding to the scanning lines 204 having less lines, data signals from the data lines 205 are less likely to be charged, as compared with the picture elements corresponding to the scanning lines 204 having more lines. Consequently, when the liquid crystal panel 100a shown in FIG. 15 is mounted to electronic equipment, brightness of images will be different in the upper display screen and the lower display screen of the electronic equipment, whereby the display quality is decreased.
Further, in the liquid crystal panel 100b shown in FIG. 16, the three lines 227 to 229 are formed in the frame-shaped wiring region 203 so as to once be led out to the fourth edge S4 side and then be led back to the first edge S1 side. Because of this, as shown in FIG. 16, the first connection lines 212 and the three lines 227 to 229 cross each other in an intersection portion B. Meanwhile, the second connection lines 213 do not cross any lines. Thereby a potential to be achieved by the upper scanning lines 204 and a potential to be achieved by the lower scanning lines 204 will be different. Consequently, likewise the liquid crystal panel 100a shown in FIG. 15, when the liquid crystal panel 100b shown in FIG. 16 is mounted to the electronic equipment, brightness of images will be different in the upper display screen and the lower display screen of the electronic equipment, whereby the display quality is decreased, likewise the aforementioned liquid crystal panel 100a. 
[Patent Document 1] JP 2003-172944 A
[Patent Document 2] JP 2005-301308 A
[Patent Document 3] JP 2003-241217 A
[Patent Document 4] JP 2004-325956 A
[Patent Document 5] JP 2005-241988 A
[Patent Document 6] WO 2008/015808 A